Field of the Invention: The present invention relates generally to semiconductor memories and, more specifically, to dynamically detecting and repairing faults in semiconductor memories by comparing multiple memory blocks against each other and then remapping failed memory blocks with unassigned spare memory blocks.
Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is structured for storing digital information in the form of a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d bit. To write (i.e., store) a bit into a memory cell, a binary memory address having portions identifying the cell""s row (the xe2x80x9crow addressxe2x80x9d) and column (the xe2x80x9ccolumn addressxe2x80x9d) is provided to addressing circuitry in the semiconductor memory to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell""s memory address, and the bit is then output from the cell.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or columns in the memory.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell""s row address is permanently stored (typically in predecoded form) on a chip on which the semiconductor memory is fabricated by programming a nonvolatile element (e.g., a group of fuses, antifuses, or FLASH memory cells) on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant row to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s row has the same row address, every cell in the failing cell""s row, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell""s column address is permanently stored (typically in predecoded form) on the chip by programming a nonvolatile element on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s column has the same column address, every cell in the failing cell""s column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
The process described above for repairing a semiconductor memory using redundant rows and columns is well known in the art, and is described in various forms in U.S. Pat. Nos. 4,459,685; 4,598,388; 4,601,019; 5,031,151; 5,257,229; 5,268,866; 5,270,976; 5,287,310; 5,355,340; 5,396,124; 5,422,850; 5,471,426; 5,502,674; 5,511,028; 5,544,106; 5,572,470; 5,572,471; 5,583,463 and 6,199,177. U.S. Pat. Nos. 6,125,067 and 6,005,813 disclose repairing a semiconductor memory using redundant subarrays.
One problem that arises with repairing semiconductor memories utilizing redundant memory elements such as rows, columns, subrows and subcolumns is that such repair is typically done at some point in the fabrication and test process. This is typically done by remapping the redundant spare memory elements to replace failed memory elements by programming nonvolatile elements (e.g., groups of fuses, antifuses, or FLASH memory cells).
In order to program these nonvolatile elements, higher than normal voltages are typically required. Thus, a relatively high voltage may be selectively applied to xe2x80x9cblowxe2x80x9d fuses or antifuses, or program FLASH memory cells. This relatively high voltage typically requires corresponding pads on an integrated circuit containing the nonvolatile elements. These pads often take up valuable real estate space on the integrated circuit.
Additionally, once the fabrication and test process is complete, memory integrated circuits are typically packaged. The packaging for these memory chips does not typically support the higher voltage connections that would be required to reprogram the memory chips.
One approach to dealing with this problem is seen in U.S. Pat. No. 5,764,577 to Johnston et al. A memory system is disclosed in that patent for performing memory repair without the use of fuses. This is done by utilizing memory elements comprised of circular coupled inverters to control memory remapping. However, the patent does not specifically disclose a provision for permanently remapping faulty memory elements discovered during the manufacturing process. Rather, the disclosure is limited to dynamically identifying faulty elements, with no provision whatsoever for permanently remapping memory elements that are discovered to be faulty during the manufacturing process.
It would be advantageous to provide a mechanism for detecting faulty memory blocks and to correct such by remapping the faulty memory blocks with spare memory blocks during the manufacturing process as well as at a later time such as, for example, while a memory is in the field.
The present invention comprises an architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), which includes circuitry for dynamically storing memory element remapping information. The memory is tested for errors, for example, with built-in self-test (BIST) or under off-chip control by, for example, the BIOS of a computer. In one embodiment of the present invention, the same test pattern of bits is written to a plurality of memory elements, such as rows or columns. The plurality of memory elements is then read back and corresponding bits are compared against each other. If corresponding bits from two memory elements are compared and do not match, then both memory elements are considered to be faulty. If corresponding bits from more than two memory elements are compared against each other and there is a mismatch, then a vote is taken in order to determine which memory element is to be considered faulty.
When errors are detected in a memory element, the memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements. This remapping utilizes a volatile latch to override nonvolatile elements. In the case where fuses or antifuses have been blown during the manufacturing process to remap memory elements, unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses. In one embodiment, this circuit includes a transistor coupled between ground and the output of an antifuse. Coupled to outputs of the transistor and the antifuse is a latch that detects and latches the status of either the antifuse or the transistor at initialization time. The output of this latch is then utilized to control whether or not a spare memory element has been remapped.